The subject matter relates to an on die termination (ODT) circuit used in a variety of semiconductor integrated circuits, and more particularly, to an ODT circuit with improved resolution.
Semiconductor circuits are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers, and workstations. Most semiconductor circuits include an input circuit configured to receive signals from outside the circuit via input pads and an output circuit configured to provide internal signals to outside the circuit via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor circuits is being gradually reduced for minimizing a time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing signal reflectivity to be more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by an external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed data transmission and distortion of output data. If semiconductor circuits receive the distorted output signal through an input terminal, problems such as a setup/hold failure and an error in decision of an input level may frequently arise.
In order to resolve the above problems, a memory circuit requiring high-speed performance employs an impedance matching circuit, which is called an ODT circuit, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed at a receiving end by a termination circuit connected in parallel to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with process, voltage and temperature (PVT) conditions. The resistance of the ODT circuit, e.g., a termination resistance at a DQ pad in a memory circuit, is calibrated using the code set resulting from the ZQ calibration. The ZQ calibration is named because the calibration is performed using a ZQ node.
The ZQ calibration in the ODT circuit will be described below.
FIG. 1 is a circuit diagram of a conventional calibration circuit of an ODT circuit for performing ZQ calibration.
Referring to FIG. 1, the conventional ODT circuit includes a first pull-up calibration resistance unit 110, a second pull-up calibration resistance unit 120, a dummy resistor 101 for pull-down calibration, a pull-down calibration resistance unit 130, a reference voltage generator 102, comparators 103 and 104, and counters 105 and 106 to perform the ZQ calibration.
The comparator 103 compares voltage level of the ZQ node and that of a reference voltage VREF to generate an up signal UP and a down signal DN. The voltage of the ZQ node is generated by connecting the first pull-up calibration resistance unit 110 and the external resistor 101 having a resistance of generally 240Ω. Here, the external resistor 101 is connected to a ZQ pin that is an external chip surface of the ZQ node. The reference voltage is generated by an internal reference voltage generator 102, and is generally set to VDDQ/2.
The pull-up counter 105 receives the up/down signals to generate binary pull-up calibration code set PCODE<0:N>. The generated binary pull-up calibration code set PCODE<0:N> turn on/off resistors connected in parallel in the first pull-up calibration resistance unit 110 to control a total resistance of the first pull-up calibration resistance unit 110. The controlled resistance of the first pull-up calibration resistance unit 110 is reflected again in the ZQ node voltage, and then the above-described operation is repeated. That is, the first pull-up calibration resistance unit 110 is calibrated such that a total resistance of the first pull-up calibration resistance unit 110 becomes identical to the resistance of the external resistor 101 of generally 240Ω (pull-up calibration).
The pull-up calibration code set PCODE<0:N>, that is binary codes generated by the above-described pull-up calibration, are input to the second pull-up calibration resistance unit 120 to determine total resistance of the second pull-up calibration resistance unit 120. Next, a pull-down calibration is performed using the comparator 104 and the pull-down counter 106 in a similar manner to the pull-up calibration. The pull-down calibration resistance unit 130 is calibrated so that a voltage of node A becomes identical to the reference voltage VREF. In other words, the pull-down calibration resistance unit 130 is calibrated so that a total resistance of the pull-down calibration resistance unit 130 becomes identical to the total resistance of the second pull-up calibration resistance unit 120 (pull-down calibration).
The binary codes PCODE<0:N> and NCODE<0:N> generated by the ZQ calibration (the pull-up calibration and the pull-down calibration) are input to pull-up and pull-down resistors (termination resistors) at the input/output pad sides. Then, the resistance of the ODT circuit, e.g., pull-up and pull-down resistance at a DQ pad side in a memory circuit, is determined. Here, the pull-up and pull-down resistors at the input/output pad sides have layouts identical to those of the pull-up and pull down calibration resistance units shown in FIG. 1.
FIG. 1 illustrates the case where both the pull-up and the pull-down calibrations are performed. Accordingly, both the pull-up calibration code set PCODE<0:N> and pull-down calibration code set NCODE<0:N> are generated to determine the total resistances of the pull-up and pull-down resistance units of the ODT circuit. However, the ODT circuits do not always have both the pull-up resistance unit and the pull-down resistance unit. For example, a semiconductor memory circuit has both the pull-up resistance unit and the pull-down resistance unit at an output driver side, however, it has only the pull-up resistance unit at an input buffer side.
When the ODT circuit has only the pull-up resistance unit at the input/output pad side, the calibration circuit of FIG. 1 also has only the pull-up calibration resistance unit 110 for generating the pull-up calibration code set PCODE<0:N>, the counter 105, and the comparator 105. The operation thereof is identical to the above-described pull-up calibration.
In the conventional calibration circuit of the ODT circuit, the ZQ node is directly connected to the comparator 103, which includes a differential amplifier. Because the voltage of the ZQ node may vary significantly according to the calibration code set PCODE<0:N>, a noise may be generated and input to the comparator 103.
In addition, because the external resistor 101 connected to the ZQ pin is connected from an outside of the system to which the ODT circuit is provided, this has the same effect as a capacitor of a great capacitance connected to the external resistor, as shown in FIG. 1 (system board capacitance). Therefore, it takes considerable time to stabilize the voltage of the ZQ pin.
The calibration circuit may always be kept in enabled state to stabilize the voltage of the ZQ pin. However, in such a case, a resistance of 480Ω, including the external resistance of 240Ω and the calibration resistance of 240Ω, always exists between the source voltage VDDQ and the ground voltage VSSQ, which may significantly increase the current consumption.